LD-DVS: Load-aware dual-speed dynamic voltage scaling Article

Poellabauer, C, Rajan, D, Zuck, R. (2009). LD-DVS: Load-aware dual-speed dynamic voltage scaling . 4(2), 112-126. 10.1504/IJES.2009.027936

cited authors

  • Poellabauer, C; Rajan, D; Zuck, R

abstract

  • The goal of dynamic voltage scaling (DVS) is to maximise the energy savings while ensuring that applications' real-time requirements are met. Accurate predictions of task run-times are necessary to compute an appropriate CPU frequency that achieves high energy savings, avoids deadlines misses and reduces the overheads caused by frequent changes between different frequency levels. This paper experimentally explores an architecture based on the XScale PXA255 processor and shows that workload-awareness is not only required for accurate predictions of utilisation, but also that in systems with a discrete number of frequency levels, the energy savings achieved by existing dual-speed DVS approaches (where an optimal theoretical CPU speed is computed and then approximated by choosing the two neighbouring discrete speed levels) are suboptimal. As a consequence, this work introduces an online approach to dual-speed DVS that formulates a model for speed selection based on the workload characteristics of the current task set and computes a frequency pair that yields the best possible energy savings for a given task set and workload. Copyright © 2009, Inderscience Publishers.

publication date

  • January 1, 2009

Digital Object Identifier (DOI)

start page

  • 112

end page

  • 126

volume

  • 4

issue

  • 2